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pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use pm5371 tudx sonet/sdh tributary unit cross connect data sheet issue 6: september 1998
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use revision history issue no. issue date details of change 6 september 1998 1. corrected some formatting problems. 2. corrected documentation errata from tudx errata document (issue 1). issue 1 errata is now obsolete. 3. issue 5 contained two different mechanical diagrams. incorrect diagram was removed. 4. all references to pqfp changed to mqfp which is a more technically correct description of the package. 5 july 1998 data sheet reformatted no change in technical content.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use i contents 1 features ....................................................................................1 2 applications .............................................................................2 3 references ..............................................................................3 4 application examples ...........................................................4 5 block diagram.........................................................................7 6 description ..............................................................................9 7 pin diagram .............................................................................10 8 pin description .....................................................................11 9 functional description ....................................................23 9.1 input bus formatter ................................................23 9.2 output bus formatter............................................23 9.3 switching element ...................................................24 9.3.1 data memories ..................................................25 9.3.2 connection memory ......................................25 9.3.3 timing generator ...........................................26 9.3.4 output multiplexer .......................................26 9.3.5 common bus interface .................................26 9.4 microprocessor interface ..................................27 10 normal mode register description.............................28 11 test features description ..............................................47 11.1 i/o test mode ...............................................................51 12 operation ................................................................................53
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use ii 12.1 basic connection memory access......................53 12.1.1 connection memory read ...........................53 12.1.2 connection memory write ..........................53 12.2 connection set up ....................................................54 12.3 idle code insertion ..................................................56 13 functional timing ................................................................58 14 absolute maximum ratings...............................................66 15 d.c. characteristics ...........................................................67 16 microprocessor interface timing characteristics ...................................................................70 17 tudx timing characteristics...........................................77 18 ordering and thermal information .............................82 19 mechanical information....................................................83
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use iii list of registers register 00h: master configuration ......................................29 register 01h: connection memory control ........................31 register 02h: clock monitor......................................................32 register 03h: master reset/revision id .................................34 register 04h: parity configuration.........................................35 register 05h: parity error interrupt enable .....................36 register 06h: parity error interrupt status ......................37 register 07h: systolic delay control ...................................38 register 08h,0ch: connection address high .......................40 register 09h,0dh: connection address low ........................42 register 0ah,0eh: connection data high ................................43 register 0bh,0fh: connection data low .................................46 register 10h: master test...........................................................49
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use iv list of figures figure 1 - 2 x 2 tudx switch array using systolic interconnect ..........................................................................4 figure 2 - 2 x 2 tudx switch array using bused interconnect ..........................................................................5 figure 3 - 2 x 2 tudx switch array using hybrid interconnect ..........................................................................6 figure 4 - overall device..............................................................7 figure 5 - each switching element ...........................................8 figure 6 - sonet sts-3 carrying vt1.5 within sts-1 ............55 figure 7 - sdh stm-1 carrying tu12 within vc3/au3 .............56 figure 8 - sdh stm-1 carrying tu12 within tug3 ..................56 figure 9 - input/output bus timing (systolic delay disabled) ..................................................................................59 figure 10- input/output bus timing (systolic delay applied to sinl/sinr) ............................................................60 figure 11- input/output bus timing (systolic delay applied to dint/dinb) ............................................................61 figure 12- input/output bus timing (systolic delay applied to doutl/doutr) ....................................................62 figure 13- input/output bus timing (systolic delay applied to soutt/soutb).....................................................64 figure 14- page timing....................................................................65 figure 15- microprocessor interface read access timing for intel mode .........................................................71 figure 16- microprocessor interface read access timing for motorola mode ...............................................72
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use v figure 17- microprocessor interface write access timing for intel mode .........................................................74 figure 18- microprocessor interface write access timing for motorola mode ...............................................75 figure 19- input timing ..................................................................78 figure 20- output timing ..............................................................80 figure 21- metric quad flat pack C mqfp (body 28x28x3.49mm) ..........................................................................83
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use vi list of tables table 1 - register memory map ..............................................27 table 2 - systolic delay control ..........................................38 table 3 - systolic array delay control .............................39 table 4 - test mode register memory map.........................47 table 5 - reading input pin values.........................................51 table 6 - forcing ouput pin values.......................................51 table 7 - connection set up ....................................................55 table 8 - idle code insertion...................................................57 table 9 - tudx maximum ratings ..............................................66 table 10 - tudx d.c. characteristics ......................................67 table 11 - microprocessor interface read access (figure 15, figure 16) ...........................................................70 table 12 - microprocessor interface write access (figure 17, figure 18) ...........................................................73 table 13 - tudx input (figure 19) ...............................................77 table 14 - tudx output (figure 20) ...........................................79 table 15 - systolic output configuration...........................79 table 16 - bused output configuration................................79 table 17 - parallel bused output configuration .............79 table 18 - ordering pm5372-ri ....................................................82
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 1 1 features a single stage, non-blocking array of time switches for cross-connecting sonet virtual tributaries (vts) or sdh tributary units (tus). provides non-blocking switching between two sts-3 (stm-1) byte serial input streams and two sts-3 (stm-1) byte serial output streams. operates from a single 19.44 mhz clock. provides parity checking on input data buses and parity generation on output data buses. allows programmable idle code insertion on a per vt or per tu basis. permits switching of any combination of sonet vt1.5, vt2, vt3, vt6, or sts-1 channels. permits switching of any combination of sdh tu11, tu12, tu2, or tu3 channels. operates in conjunction with the pm5361 tudx sonet/sdh tributary unit payload processor which aligns sonet vts or sdh tus such that they can be switched by the tudx. cascadable in a systolic or bused manner to allow larger switching arrays to be implemented. provides control outputs that are programmable on a per timeslot basis to facilitate construction of larger switching arrays. provides programmable delay to match data skew in the systolic array application. provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. low power, +5 volt, cmos technology. device has ttl compatible inputs and outputs. 160 pin metric quad flat pack (mqfp) package.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 2 2 applications sonet and sdh wideband cross-connects sonet and sdh add-drop and terminal multiplexers
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 3 3 references 1. american national standard for telecommunications - digital hierarchy - optical interface rates and formats specification, ansi t1.105-1988. 2. bell communications research - sonet transport systems: common generic criteria, tr-tsy-000253, issue 1, september 1989. 3. ccitt blue book, recommendation g.708 - "network node interface for the synchronous digital hierarchy", volume iii, fascicle iii.4, 1988. 4. ccitt blue book, recommendation g.709 - "synchronous multiplexing structure", volume iii, fascicle iii.4, 1988. 5. ccitt study group xviii, report r 33 - "recommendations drafted by working party xviii/7" (digital hierarchies) to be approved in 1990 including revised draft recommendations g.708 and g.709", june 1990. 6. bell communications research - sonet transport systems: common generic criteria, ta-nwt-000253, issue 6, september 1990.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 4 4 application examples larger switching arrays can be constructed in a variety of manners using arrays of tudx devices. systolic or bused interconnect methods can be used, or a hybrid of the two approaches. figure 1 - 2 x 2 tudx switch array using systolic interconnect '0' '0' '0' '0' '5' '15' '10' '15' '15' '15' '5' '10' tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ofp ifp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ofp ifp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ofp ifp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ofp ifp sinr doutr sobeb aobeb systolic interconnect of tudx devices is illustrated above. in this 2 x 2 array of devices, pcm data is distributed left to right and gathered top to bottom with the pcm data being re-timed as it passes through each device. each pcm data bus drives a single device, regardless of the size of the array and thus systolic interconnect allows large arrays to be implemented without the use of additional devices. in this example no systolic delay is required for the upper left hand and lower right hand tudx in the array. the systolic delay control register of the lower left hand tudx is programmed to insert a 5 clock period delay in the dint/dinb buses, and a 5 clock period delay in the doutl/doutr buses. the
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 5 systolic delay control register of the upper right hand tudx is programmed to insert a 5 clock period delay in the sinl/sinr buses, and the soutt/soutb buses. figure 2 - 2 x 2 tudx switch array using bused interconnect '5' '5' '0' '5' '0' '0' '0' '5' tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ifp ofp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ifp ofp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ifp ofp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ifp ofp sinr doutr sobeb aobeb bused interconnect of tudx devices is illustrated above. in this 2 x 2 array of devices, pcm data is distributed left to right on a common bus and gathered top to bottom using a wired-or type bus. using this interconnect approach, additional devices must be used to drive the distribution bus and sample the wired-or bus. to maximize the size of array that can be achieved using a wired- or bus, the aoutl and aoutr buses may be parallel connected with the doutl and doutr buses on a bit by bit basis in order to provide higher drive levels. due to the higher fan out of these buses, and the rc delay on the wired- or bus, this approach cannot be extended to very large arrays without additional circuitry. this bused array approach provides the minimum data delay through the array (when a cross connection is made between the dint/dinb buses and
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 6 the doutl/doutr buses) of nominally 275 clock periods versus 285 clock periods using the systolic array approach. figure 3 - 2 x 2 tudx switch array using hybrid interconnect '0' '0' '10' '10' '0' '0' '0' '0' '5' '5' tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ifp ofp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ifp ofp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ifp ofp sinr doutr sobeb aobeb tudx sinl doutl dint soutt ofseb dinb soutb odeb sfp sclk ifp ofp sinr doutr sobeb aobeb a hybrid approach using a mix of bused and systolic interconnect of tudx devices is illustrated above. in this 2 x 2 array of devices, pcm data is distributed left to right on a common bus and gathered top to bottom with the pcm data being re-timed as it passes through each device. using this interconnect approach, additional devices must be used to drive the distribution buses. this approach overcomes the rc delay of the wired-or bus by using systolic interconnect from top to bottom. in this example the systolic delay control registers in the two bottom tudx devices are programmed to delay the dint/dinb buses by five clock periods to match the delay seen at the sinl/sinr inputs to these devices.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 7 5 block diagram figure 4 - overall device rstb cs1b cs2b rdb wrb ale a[4:0] mbeb d[7:0] ifp ofp dinb[8:0] dint[8:0] sobeb sfp odeb coutl doutl[8:0] coutr doutr[8:0] output bus formatter switching input bus formatter input bus form- atter micro interface ofseb sinl[8:0] sinr[8:0] soutt[8:0] soutb[8:0] intb page aoutl[8:0] aoutr[8:0] aobeb time switch time switch time switch time switch element switching element sclk
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 8 figure 5 - each switching element dinb[7:0] dout[7:0] dint[7:0] data memory rstb tstb bsb rdb wrb trsb a[1:0] d[7:0] sclk sfp cout pcm write address read address read address pcm idle code control timing connection memory timing generator output mux data memory common bus interface pcm pcm make page
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 9 6 description the pm5371 tudx sonet/sdh tributary unit cross-connect is a monolithic integrated circuit that allows non-blocking switching of tributaries within two sonet sts-3 or sdh stm-1 streams. any tributary entering on either stream can be connected to any same size tributary within either outgoing stream. the tudx can be programmed to cross-connect a mix of sonet vt1.5, vt2, vt3, vt6, or sts-1 channels or sdh tu11, tu12, tu2, or tu3 channels. programmable idle code can also be inserted into any of these channels. the tudx allows cross-connection of up to 168 vt1.5 or tu11 streams, up to 126 vt2 or tu12 streams, or up to 42 vt6 or tu2 streams or any legal mix as permitted by the sonet or sdh mappings. the tudx operates in conjunction with the pm5361 tupp sonet/sdh tributary unit payload processor which aligns sonet vts or sdh tus such that they can be switched by the tudx. larger switches can be constructed using arrays of tudx devices. the tudx is cascadable in a systolic or bused manner and provides programmable control outputs that are useful in constructing larger switching arrays. no high speed clocks are required as the tudx operates from a single 19.44 mhz clock. parity checking is provided on input data buses and parity generation is provided on output data buses. the tudx is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. the tudx is implemented in low power, +5 volt, cmos technology. it has ttl compatible inputs and outputs and is packaged in a 160 pin metric quad flat pack (mqfp) package.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 10 7 pin diagram the tudx is packaged in an 160 pin mqfp package having a body size of 28 mm by 28 mm and a pin pitch of 0.65 mm. index pin 1 pin 160 pm5371 tudx (top view) pin 120 pin 121 pin 81 pin 80 pin 40 pin 41 odeb aobeb dint[0] dint[1] dint[2] dint[3] dint[4] dint[5] dint[6] dint[7] dint[8] a[0] a[1] a[2] a[3] a[4] cs1b cs2b dinb[0] vddi vssi dinb[1] dinb[2] dinb[3] dinb[4] dinb[5] dinb[6] dinb[7] dinb[8] sobeb d[0] d[1] d[2] d[3] vsso vddo d[4] d[5] d[6] d[7] vsso ifp ofp coutr vsso vddo soutb[6] soutb[8] soutb[7] soutb[5] soutb[4] soutb[3] soutb[2] soutb[1] soutb[0] vsso wrb_rwb rdb_e ale vsso vddo sclk vddi vssi rstb mbeb intb vddo soutt[8] soutt[7] soutt[6] soutt[5] soutt[4] soutt[3] soutt[2] soutt[1] soutt[0] coutl vsso vddo
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 11 8 pin description pin name type pin no. function sclk input 97 the system clock (sclk) provides timing for tudx internal operation. sclk is a 19.44 mhz, nominally 50% duty cycle clock. vclk the test vector clock (vclk) provides timing for tudx production test. sfp input 42 the system frame pulse (sfp) determines the frame boundaries on the dint[8:0] and dinb[8:0] buses (and sinl[8:0] and sinr[8:0] buses) when ofseb is high. sfp determines the frame boundaries on the soutt[8:0] and soutb[8:0] buses when ofseb is low. sfp must be brought high once every frame (125 s) to mark the first c1 byte of the transport envelope frame of the buses in question. in systolic applications where ofseb is high, sfp marks the c1 byte of the sinl[8:0] and sinr[8:0] buses (or the dint[8:0] and dinb[8:0] buses) after the programmable systolic delay has been inserted. see the application examples and functional timing sections for more information. sfp is sampled on the rising edge of sclk. ofseb input 160 the active low output frame synchronization enable (ofseb) signal selects the system frame alignment marked by sfp. when ofseb is high, sfp is coincident with the input frame pulse (ifp). when ofseb is low, sfp is coincident with the output frame pulse (ofp). in most applications, ofseb should be held high. the ofseb input has an integral pull up resistor.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 12 pin name type pin no. function ifp output 82 the input frame pulse (ifp) marks the frame boundaries on the dint[8:0] and dinb[8:0] buses (or sinl[8:0] and sinr[8:0] buses). ifp pulses high for a single sclk period to mark the first c1 byte of the transport envelope frame of the buses in question. in systolic array applications, ifp marks the frame boundaries of the sinl[8:0] and sinr[8:0] buses (or the dint[8:0] and dinb[8:0] buses) after the programmable systolic delay has been inserted. see the application examples and functional timing sections for more information. ifp is updated on the rising edge of sclk. ofp output 83 the output frame pulse (ofp) marks the frame boundaries on the soutt[8:0] and soutb[8:0] buses. ofp pulses high for a single sclk period to mark the first c1 byte of the transport envelope frame. ofp is updated on the rising edge of sclk. dint[0] dint[1] dint[2] dint[3] dint[4] dint[5] dint[6] dint[7] dint[8] input 3 4 5 6 7 8 9 10 11 the top data input bus (dint[8:0]) carries sonet/sdh frame data in byte serial format. the dint[8] bit is a parity bit which is not passed through the tudx. the tudx may be configured to check for even or odd input bus parity and generate interrupts when parity errors occur. the dint[8:0] bus is sampled on the rising edge of sclk.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 13 pin name type pin no. function dinb[0] dinb[1] dinb[2] dinb[3] dinb[4] dinb[5] dinb[6] dinb[7] dinb[8] input 19 22 23 24 25 26 27 28 29 the bottom data input bus (dinb[8:0]) carries sonet/sdh frame data in byte serial format. the dint[8] bit is a parity bit which is not passed through the tudx. the tudx may be configured to check for even or odd input bus parity and generate interrupts when parity errors occur. the dinb[8:0] bus is sampled on the rising edge of sclk. doutl[0] doutl[1] doutl[2] doutl[3] doutl[4] doutl[5] doutl[6] doutl[7] doutl[8] output/ od output 128 131 133 137 139 145 147 151 153 the left data output bus (doutl[8:0]) carries sonet/sdh frame data in byte serial format. the doutl[8] bit is a parity bit which is generated by the tudx. the tudx may be configured to generate even or odd parity. the doutl[8:0] bus is updated on the rising edge of sclk. doutl may be configured as a normal output or as an open drain output, the latter mode being useful for constructing larger switching arrays. doutr[0] doutr[1] doutr[2] doutr[3] doutr[4] doutr[5] doutr[6] doutr[7] doutr[8] output/ od output 73 71 67 65 61 57 53 51 48 the right data output bus (doutr[8:0]) carries sonet/sdh frame data in byte serial format. the doutr[8] bit is a parity bit which is generated by the tudx. the tudx may be configured to generate even or odd parity. the doutr[8:0] bus is updated on the rising edge of sclk. doutr may be configured as a normal output or as an open drain output, the latter mode being useful for constructing larger switching arrays.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 14 pin name type pin no. function aoutl[0] aoutl[1] aoutl[2] aoutl[3] aoutl[4] aoutl[5] aoutl[6] aoutl[7] aoutl[8] output/ od output 127 130 132 136 138 144 146 150 152 the left auxiliary data output bus (aoutl[8:0]) carries sonet/sdh frame data in byte serial format. the aoutl[8] bit is a parity bit which is generated by the tudx. the tudx may be configured to generate even or odd parity. the aoutl[8:0] bus is updated on the rising edge of sclk. aoutl may be configured as a normal output or as an open drain output, the latter mode being useful for constructing larger switching arrays. the aoutl output bus carries the same information as the doutl bus and the two buses may be parallel connected on a bit by bit basis when additional output drive is required. the aoutl bus is held in a high impedance mode to save power when not enabled. aoutr[0] aoutr[1] aoutr[2] aoutr[3] aoutr[4] aoutr[5] aoutr[6] aoutr[7] aoutr[8] output/ od output 74 72 68 66 62 58 54 52 49 the right auxiliary data output bus (aoutr[8:0]) carries sonet/sdh frame data in byte serial format. the aoutr[8] bit is a parity bit which is generated by the tudx. the tudx may be configured to generate even or odd parity. the aoutr[8:0] bus is updated on the rising edge of sclk. aoutr may be configured as a normal output or as an open drain output, the latter mode being useful for constructing larger switching arrays. the aoutr output bus carries the same information as the doutr bus and the two buses may be parallel connected on a bit by bit basis when additional output drive is required. the aoutr bus is held in a high impedance mode to save power when not enabled. aobeb input 2 the active low auxiliary output bus enable (aobeb) signal enables the aoutl and aoutr when low. when aobeb is high, the aoutl and aoutr output buses are held in a high impedance mode to save power. the aobeb input has an integral pull up resistor.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 15 pin name type pin no. function sinl[0] sinl[1] sinl[2] sinl[3] sinl[4] sinl[5] sinl[6] sinl[7] sinl[8] input 121 122 123 124 125 156 157 158 159 the left systolic input bus (sinl[8:0]) carries sonet/sdh frame data in byte serial format. the sinl[8] bit is a parity bit which is not passed through the tudx. the tudx may be configured to check for even or odd input bus parity and generate interrupts when parity errors occur. the sinl[8:0] bus is sampled on the rising edge of sclk. data on the sinl[8:0] bus is re-timed and may be routed to the doutl[8:0] in place of information switched from the dint[8:0] bus, and is provided for constructing larger switching arrays using systolic data flow. sinr[0] sinr[1] sinr[2] sinr[3] sinr[4] sinr[5] sinr[6] sinr[7] sinr[8] input 80 79 78 77 76 46 45 44 43 the right systolic input bus (sinr[8:0]) carries sonet/sdh frame data in byte serial format. the sinr[8] bit is a parity bit which is not passed through the tudx. the tudx may be configured to check for even or odd input bus parity and generate interrupts when parity errors occur. the sinr[8:0] bus is sampled on the rising edge of sclk. data on the sinr[8:0] bus is re-timed and may be routed to the doutr[8:0] in place of information switched from the dinb[8:0] bus, and is provided for constructing larger switching arrays using systolic data flow. soutt[0] soutt[1] soutt[2] soutt[3] soutt[4] soutt[5] soutt[6] soutt[7] soutt[8] output 117 116 115 114 113 112 111 110 109 the left systolic output bus (soutt[8:0]) carries sonet/sdh frame data in byte serial format. the soutt[8] bit is a parity bit which is generated by the tudx. the tudx may be configured to generate even or odd parity. the soutt[8:0] bus is updated on the rising edge of sclk. the soutt[8:0] bus carries a re-timed copy of the information sampled on the dint[8:0] bus and is provided for constructing larger switching arrays using systolic data flow. the soutt bus can be disabled to save power when not used.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 16 pin name type pin no. function soutb[0] soutb[1] soutb[2] soutb[3] soutb[4] soutb[5] soutb[6] soutb[7] soutb[8] output 95 94 93 92 91 90 89 88 87 the right systolic output bus (soutb[8:0]) carries sonet/sdh frame data in byte serial format. the soutb[8] bit is a parity bit which is generated by the tudx. the tudx may be configured to generate even or odd parity. the soutb[8:0] bus is updated on the rising edge of sclk. the soutb[8:0] bus carries a re-timed copy of the information sampled on the dinb[8:0] bus and is provided for constructing larger switching arrays using systolic data flow. the soutb bus can be disabled to save power when not used. sobeb input 30 the active low systolic output bus enable (sobeb) signal enables the soutt and soutb output buses when low. when sobeb is high, the soutt and soutb output buses are held in a high impedance mode to save power. the sobeb input has an integral pull up resistor. coutl output 120 the left control output signal (coutl) is a software programmable control stream (on a per timeslot basis) that can be used for controlling external hardware when constructing larger switching arrays. after reset, coutl defaults to always high until otherwise programmed. coutl is updated on the rising edge of sclk. coutr output 84 the right control output bus (coutr) is a software programmable control stream (on a per timeslot basis) that can be used for controlling external hardware when constructing larger switching arrays. after reset, coutr defaults to always high until otherwise programmed. coutr is updated on the rising edge of sclk.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 17 pin name type pin no. function odeb input 1 the active low open drain enable (odeb) signal configures the doutl and doutr output buses as open drain outputs when low. when odeb is high, the doutl and doutr output buses are configured as normal outputs. the odeb input has an integral pull up resistor. page input 41 the page select (page) signal selects the connection memory pages that are used to control connections within the tudx. when page is low, connection memory page 0 of each switching element is used. when page is high, connection memory page 1 of each switching element is used. the page input is sampled on the rising edge of sclk. internally, a change in the active connection memory page is held off until the next switching frame boundary (a delay of up to approximately 14 us). while such a page swap is pending, accesses to the connection memory by the microprocessor should be avoided. such a pending page swap results in a connection memory busy indication which can be polled. the page input has an integral pull down resistor. mbeb input 105 the active low motorola bus enable (mbeb) signal configures the tudx for motorola bus mode where the rdb/e signal functions as e, and the wrb/rwb signal functions as rwb. when mbeb is high, the tudx is configured for intel bus mode where the rdb/e signal functions as rdb. the mbeb input has an integral pull up resistor. cs1b input 17 the active low chip select #1 (cs1b) signal is low during tudx register accesses. if cs1b and cs2b are not required (i.e., registers accesses are controlled using the rdb and wrb signals only), cs1b and cs2b must be connected to an inverted version of the rstb input.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 18 pin name type pin no. function cs2b input 18 the active low chip select #2 (cs2b) signal is low during tudx register accesses. if cs1b and cs2b are not required (i.e., registers accesses are controlled using the rdb and wrb signals only), cs1b and cs2b must be connected to an inverted version of the rstb input. rdb input 102 the active low read enable (rdb) signal is low during tudx register read accesses while in intel bus mode (mbeb = 1). the tudx drives the d[7:0] bus with the contents of the addressed register while rdb, cs1b, and cs2b are low. e input 102 the active high external access (e) signal is high during tudx register access while in motorola bus mode (mbeb = 0). wrb input 101 the active low write strobe (wrb) signal is low during a tudx register write accesses while in intel bus mode (mbeb = 1). the d[7:0] bus contents are clocked into the addressed register on the rising wrb edge while cs1b and cs2b are low. rwb the read/write select (rwb) signal selects between tudx register read and write accesses while in motorola bus mode (mbeb = 0). the tudx drives the d[7:0] bus with the contents of the addressed register while cs1b and cs2b are low and rwb and e are high. the d[7:0] bus contents are clocked into the addressed register on the falling e edge while cs1b and cs2b and rwb are low.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 19 pin name type pin no. function d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] i/o 31 32 33 34 37 38 39 40 the bidirectional data bus (d[7:0]) is used during tudx register read and write accesses. a[0] a[1] a[2] a[3] a[4]/trs input 12 13 14 15 16 the address bus (a[4:0]) selects specific registers during tudx register accesses. the test register select (trs) signal discriminates between normal and test mode register accesses. trs is high during test mode register accesses, and is low during normal mode register accesses. the trs input has an integral pull down resistor. rstb input 104 the active low reset (rstb) signal provides an asynchronous tudx reset. rstb is a schmitt triggered input with an integral pull up resistor. ale input 103 the address latch enable (ale) is active high and latches the address bus (a[4:0]) and trs when low. when ale is high, the internal address latches are transparent. it allows the tudx to interface to a multiplexed address/data bus. the ale input has an integral pull up resistor. intb od output 106 the active low interrupt (intb) signal goes low when a tudx interrupt source is active. intb returns high when the interrupt is acknowledged via an appropriate register access. the intb output is an open drain output.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 20 pin name type pin no. function vddi1 vddi2 vddi3 vddi4 power 20 60 100 140 the core power (vddi) pins should be connected to a well decoupled +5 v dc in common with vddo. vssi1 vssi2 vssi3 vssi4 ground 21 59 99 141 the core ground (vssi) pins should be connected to gnd in common with vsso. vddo1 vddo2 vddo3 vddo4 vddo5 vddo6 vddo7 vddo8 vddo9 vddo10 vddo11 vddo12 vddo13 vddo14 power 36 47 55 63 69 86 96 108 119 126 135 143 148 154 the pad ring power (vddo) pins should be connected to a well decoupled +5 v dc in common with vddi.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 21 pin name type pin no. function vsso1 vsso2 vsso3 vsso4 vsso5 vsso6 vsso7 vsso8 vsso9 vsso10 vsso11 vsso12 vsso13 vsso14 vsso15 vsso16 ground 35 50 56 64 70 75 81 85 98 107 118 129 134 142 149 155 the pad ring ground (vsso) pins should be connected to gnd in common with vssi. notes on pin description: 1. all tudx inputs and bidirectionals present minimum capacitive loading and operate at ttl logic levels. 2. all tudx digital outputs and bidirectionals have 2 ma drive capability, except the intb, soutt[8:0], soutb[8:0] outputs and d[7:0] bidirectionals, which have 4 ma drive capability, and the doutl[8:0], doutr[8:0], aoutl[8:0] and aoutr[8:0] outputs, which have 8 ma drive capability. 3. the vsso and vssi ground pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the tudx.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 22 4. the vddo and vddi power pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the tudx.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 23 9 functional description 9.1 input bus formatter the input bus formatter captures data sampled on the dint and dinb buses and distributes this data to the two switching elements within the tudx. the input bus formatter also re-times this captured data, delaying it 5 clock cycles and outputs copies of the information from the dint and dinb buses on the soutt and soutb buses, respectively. when systolic interconnect is not used, the soutt and soutb buses can be held in a high impedance mode to save power by strapping the sobeb input appropriately. for systolic array applications, a programmable delay element provides additional delay of 5, 10, or 15 clock cycles in the dint and dinb data paths or in the soutt and soutb data paths. for more information on the systolic array application, see the application examples section. the input bus formatter also provides timing signals for the other blocks within the tudx. the system clock, sclk, is buffered and distributed to the switching elements and the output bus formatter. frame pulses for the incoming and outgoing data streams, ifp and ofp, are generated with alignment dictated by the system frame pulse input, sfp. these frame pulses are buffered and distributed to the switching elements. one can select whether the sfp input will generate a coincident ifp or ofp pulse using the ofseb configuration input. this option is useful when constructing larger switches using arrays of tudx devices. the input bus formatter generates the ifp and ofp outputs. proper generation of ifp and ofp requires that the input bus formatter be initialized once per sonet/sdh frame (125 s) by a pulse on the sfp input. in the absence of a periodic sfp input, outputs ifp and ofp are not generated correctly. 9.2 output bus formatter the output bus formatter selects the data to be output on the doutl and doutr buses. this data is gathered from the switching elements or the sinl and sinr buses, on a per timeslot basis, as programmed within the switching elements. the output bus formatter also drives the coutl and coutr outputs with control signals that are programmable, on a per timeslot basis, via the switching elements. the delay from the sinl or sinr buses to the doutl or doutr buses is 5 clock cycles. the delay from the dint or dinb buses to the doutl or doutr buses for a straight through connection (from each input timeslot to its equivalent output timeslot) is 275 clock cycles (corresponding to
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 24 one sonet sts-3 or sdh stm-1 row of 270 bytes plus 5 clock cycles of re- timing delay). for systolic array applications, a programmable delay element provides an additional delay of 5, 10 or 15 clock cycles in the sinl and sinr data paths or in the doutl and doutr data paths. the output bus formatter can be configured to drive the doutl and doutr buses rail to rail or drive the doutl and doutr buses as open drain outputs. the open drain output option is selected by strapping the odeb input appropriately. a second set of output buses, the aoutl and aoutr buses, carry the same data as the doutl and doutr buses, respectively. these pairs of buses can be strapped together on a bit by bit basis in order to provide higher drive capability. this is particularly useful in implementing wired-or type output buses. when not required, the aoutl and aoutr buses can be held in a high impedance mode to save power by strapping the aobeb input appropriately. 9.3 switching element each switching element implements two single stage, non-blocking time switches that each process an sts-3 or stm-1 rate stream. the channelization of each time switch corresponds to 9 byte columns within the sonet/sdh frame. thus the basic switching granularity is 576 kbit/s (9 x 64 kbit/s). the frame rate of each time switch corresponds to 1/9th of the sonet/sdh frame rate. the frame rate is thus 13.89 us (125 us 9). the frame processed by each time switch corresponds to 270 byte rows within the sonet/sdh frame. two time switches that connect to a common output bus are grouped within each switching element such that they can share a common connection memory. cross-connection of the various sizes of vts (or tus) is accomplished by setting up group connections. a vt1.5, for example, occupies three 9 byte columns within the sonet/sdh frame and thus a vt1.5 cross-connection can be set up by making three connections of 576 kbit/s each. a tu12, in contrast, occupies four 9 byte columns and thus a tu12 cross-connection can be set up by making four connections of 576 kbit/s each. the time switches are double buffered so as to exhibit constant frame delay which preserves byte sequence integrity during group connections, regardless of the size and routing of the group connection. note that the switching elements assume that the tributaries to be cross- connected occupy fixed 9 byte columns within the sonet sts-3 or sdh stm-1 frame. in order to cross-connect vt1.5, vt2, vt3, or vt6 tributaries within an sts-3 stream or tu11, tu12, tu2, or tu3 tributaries within an stm-1 stream, the sts-3 or stm-1 stream must be preprocessed with the pm5361 tupp or an equivalent circuit. such processing must ensure that all sts-1 or au-3 or au-4
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 25 pointer adjustments are absorbed into vt or tu pointer adjustments such that the resulting sts-3 or stm-1 frame has its vts or tus occupying fixed, appropriately phase aligned positions with respect to the overall transport envelope frame, ready for switching. the tudx consists of two switching elements, each containing two time switches, which results in a 2 by 2 array of time switches. data from each of the dint and dinb buses is distributed and written into the two time switches in the corresponding row. data is collected for output on the doutl and doutr buses from each of the two time switches in the corresponding column or switching element, or from the associated sinl or sinr bus. the source of data is programmable on a per timeslot basis within the switching elements. as only one time switch in a column can source data during a given timeslot, time switch outputs are powered down, rather than outputting data, 50% of the time. in addition to implementing cross-connections, the switching elements are also capable of inserting programmable idle code into outgoing timeslots. this idle code is arbitrarily programmable on a per timeslot basis and thus through proper programming, a fixed, arbitrary idle code can be inserted into any outgoing vt or tu. this capability can be used to insert tributary path ais or to insert fixed codes used for system diagnostic purposes. the switching elements are implemented in a classical manner with each having a pair of data memories, a common connection memory, timing generator, output multiplexer, and common bus interface. 9.3.1 data memories the data memories each consist of two 270 x 8 rams implementing a double buffered switch core. during each switching frame, data is written into sequential locations in one page of memory, and read from the other page of memory based on a list of addresses provided by the connection memory. at each switching frame boundary (every 270 bytes) the function of the two memory pages is reversed. the data memory is 8 bits wide to allow byte wide data to be routed through the switching element. two data memories are required, one for each of the input buses connected to the switching element. 9.3.2 connection memory the connection memory consists of a double buffered 270 x 13 ram. during each switching frame, information is sequentially read from the active memory page and used to generate the read addresses for the data memory and control the output multiplexer. either connection memory can be written to or read from
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 26 via the common bus interface and thus its contents are programmable. in this manner, the switching action of the data memory and output multiplexer are programmable on a per timeslot basis. normally one would only write to the inactive page, performing all the programming required to implement ones desired connections, and then trigger a page swap at a frame boundary. use of a double buffered connection memory and active page swapping allows tributary connections (which are implemented as group connections of 576 kbit/s timeslots) to be coherently made or broken. 9.3.3 timing generator the timing generator consists of a frame counter and clock dividers. buffered versions of the various derived clocks are distributed to other blocks within the switching element as are several phase delayed versions of the frame count, as required in such a pipelined processing structure. 9.3.4 output multiplexer the output multiplexer consists of logic that selects the source of information to be output from the switching element. such selection is controlled on a per timeslot basis by the connection memory and is thus programmable. output data can be routed from the data memory, from the lower order bits of the connection memory, or a null value can be inserted when no connection is being made. the null value is chosen on the fly to minimize power dissipation. the ability to source data from the connection memory itself is how programmable idle code insertion is provided. during those timeslots when programmable idle code is being inserted or no connection is being made through the switching element, the reading of data from the data memory is suppressed in order to save power. in addition to its selection function, the output multiplexer also re-times control signals sourced by the connection memory that are used to control the output bus formatter of the complete device. 9.3.5 common bus interface the common bus interface allows microprocessor access to the switching element connection memory. access is indirect, via registers located in the common bus interface. each connection memory access takes up to eight sclk cycles to complete as circuitry waits for opportunities when the connection memory locations in question are not being accessed during the normal course of switching element operation.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 27 9.4 microprocessor interface the microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. the normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the tudx. the register set is accessed as follows: table 1 - register memory map address register 00h tudx master configuration 01h tudx connection memory control 02h tudx clock monitor 03h tudx master reset/revision id 04h tudx parity configuration 05h tudx parity error interrupt enable 06h tudx parity error interrupt status 07h tudx systolic delay control 08h left switch element connection address high 09h left switch element connection address low 0ah left switch element connection data high 0bh left switch element connection data low 0ch right switch element connection address high 0dh right switch element connection address low 0eh right switch element connection data high 0fh right switch element connection data low 10h tudx master test 11h-1fh reserved for test for all register accesses, cs1b and cs2b must be low.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 28 10 normal mode register description normal mode registers are used to configure and monitor the operation of the tudx. normal mode registers (as opposed to test mode registers) are selected when trs (a[4]) is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic 0. reading back unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the tudx to determine the programming state of the block. 3. writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect tudx operation unless otherwise noted.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 29 register 00h: master configuration bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w selen 0 bit 2 r/w seren 0 bit 1 r/w coutlen 0 bit 0 r/w coutren 0 this register is used to enable the switching elements and the generation of the programmable control output signals. coutlen: the coutlen bit enables the generation of the coutl signal under control of the left switching element; the switching element that routes between the dint and doutl buses, or dinb and doutl buses, respectively. after reset, the coutl signal is forced high, until the coutlen bit is set high. coutren: the coutren bit ernables the generation of the coutr signal under control of the right switching element; the switching element that routes between the dint and doutr buses, or dinb and doutr buses, respectively. after reset, the coutr signal is forced high, until the coutren bit is set high. selen: the selen bit enables operation of the left switching element (the switching element that routes between the dint and doutl buses, or dinb and doutl buses, respectively). after reset, the left switching element is held reset to save power, until the selen bit is set high. seren: the seren bit enables operation of the right switching element (the switching element that routes between the dint and doutr buses, or dinb
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 30 and doutr buses, respectively). after reset, the right switching element is held reset to save power, until the seren bit is set high. note that a switching element cannot be programmed until it is enabled. while a switching element is disabled, the output bus formatter will not select it as a source of data, thus passing through data from the sinl or sinr bus, as appropriate.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 31 register 01h: connection memory control bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r apage x bit 1 r epage x bit 0 r/w ipage 0 this register is used to control and monitor the selection of the active connection memory page. ipage: the ipage bit is used to internally select the active connection memory page. when ipage is set high, page 1 is selected. when ipage is cleared low, page 0 is selected, provided that the external page input is also low. epage: the epage bit can be read to determine the state of the external page input. apage: the apage bit can be read to determine the active connection memory page. apage is the logical or of the ipage bit and the page input (which can be read via the epage bit).
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 32 register 02h: clock monitor bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r dinba x bit 2 r dinta x bit 1 r sfpa x bit 0 r sclka x this register is used to monitor the integrity of tudx timing input signals. sclka: the sclka bit indicates that sclk is active when high. sclka is set high by a low to high transition on sclk and is set low immediately following a read of this register. this bit is intended to be polled to detect a system failure that freezes the sclk signal. sfpa: the sfpa bit indicates that sfp is active when high. sfpa is set high by a sclk sampled low to high transition on sfp and is set low immediately following a read of this register. this bit is intended to be polled to detect a system failure that freezes the sfp signal. dinta: the dinta bit indicates that dint bus is active when high. dinta is set high when all bits of the dint[8:0] bus have changed low to high after sampled by sclk and is set low immediately following a read of this register. this bit is intended to be polled to detect a system failure that freezes any of the dint[8:0] bits. dinba: the dinba bit indicates that dinb bus is active when high. dinba is set high when all bits of the dinb[8:0] bus have changed low to high after sampled by sclk and is set low immediately following a read of this register.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 33 this bit is intended to be polled to detect a system failure that freezes any of the dinb[8:0] bits.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 34 register 03h: master reset/revision id bit type function default bit 7 r/w reset 0 bit 6 r id[6] 0 bit 5 r id[5] 0 bit 4 r id[4] 0 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 0 this register allows the revision of the tudx to be read by software permitting graceful migration to support for newer, feature enhanced versions of the tudx, should revision of the tudx occur. this register also allows the tudx to be reset. id[6:0]: the id bits can be read to provide a binary tudx revision number. reset: the reset bit allows the tudx to be reset under software control. if the reset bit is a logic 1, the entire tudx is held in reset. this bit is not self- clearing; therefore, a logic 0 must be written to bring the tudx out of reset. holding the tudx in a reset state effectively puts it into a low power, stand-by mode. a hardware reset clears the reset bit, thus de-asserting the software reset.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 35 register 04h: parity configuration bit type function default bit 7 r/w toddo 0 bit 6 r/w boddo 0 bit 5 r/w loddo 0 bit 4 r/w roddo 0 bit 3 r/w toddi 0 bit 2 r/w boddi 0 bit 1 r/w loddi 0 bit 0 r/w roddi 0 this register is used to configure the parity polarity expected on input buses and generated on output buses. roddi, loddi, boddi, toddi: these bits configure the parity expected on input buses. when high, odd parity is expected. when low, even parity is expected. the roddi bit configures the sinr bus, the loddi bit configures the sinl bus, the boddi bit configures the dinb bus, and the toddi bit configures the dint bus. roddo, loddo, boddo, toddo: these bits configure the parity generated on output buses. when high, odd parity is generated. when low, even parity is generated. the roddo bit configures the doutr bus, the loddo bit configures the doutl bus, the boddo bit configures the soutb bus, and the toddo bit configures the soutt bus. note that bad parity can be introduced for diagnostic purposes by manipulating these bits.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 36 register 05h: parity error interrupt enable bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r/w tpere 0 bit 2 r/w bpere 0 bit 1 r/w lpere 0 bit 0 r/w rpere 0 this register is used to enable parity errors to generate interrupts. rpere, lpere, bpere, tpere: these bits enable parity errors on their respective input buses to generate interrupts. when high, parity error interrupt generation is enabled. when low, parity error interrupt generation is disabled, however, the parity error indications may still be polled. the rpere bit configures the sinr bus, the lpere bit configures the sinl bus, the bpere bit configures the dinb bus, and the tpere bit configures the dint bus.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 37 register 06h: parity error interrupt status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r tperi x bit 2 r bperi x bit 1 r lperi x bit 0 r rperi x this register is used to identify the source of a parity error interrupt and acknowledge such an interrupt. rperi, lperi, bperi, tperi: these bits are set high when a parity error on their respective input buses is detected. if enabled, an interrupt will also occur. these bits are cleared low immediately following a read of this register causing any active interrupt to be de-asserted. these bits are latching and will remain high following the detection of a single parity error until this register is read. these bits retain their event capture functionality when interrupt generation is disabled and may be polled to detect parity errors. the rperi bit monitors the sinr bus, the lperi bit monitors the sinl bus, the bperi bit monitors the dinb bus, and the tperi bit monitors the dint bus.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 38 register 07h: systolic delay control bit type function default bit 7 unused x bit 6 unused x bit 5 r/w souten 0 bit 4 r/w sinen 0 bit 3 r/w douten 0 bit 2 r/w dinen 0 bit 1 r/w ds1 0 bit 0 r/w ds0 0 this register is used to control the delay inserted into the sout, sin, dout, and din data paths. this feature is used in systolic array applications to match data skew at the array boundaries for up to a 4 x 4 array without using external components. souten, sinen, douten, dinen: these bits control the programmable delay elements, one of which is shared between din and sout, the other between sin and dout. the delay is inserted when these bits are set high. it is not appropriate to set both dinen and souten high simultaneously, nor sinen and douten. the delay value for both delay elements is controlled by the ds1 and ds0 bits. ds1, ds0: the ds1 and ds0 bits select the delay value for both delay elements as described in the following table: table 2 - systolic delay control ds1 ds0 delay value 0 0 0 not appropriate if any enable bits are logic 1. 01 5 10 10 11 15
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 39 when constructing a 4 x 4 systolic array, program the individual tudx devices with the following binary codes: table 3 - systolic array delay control 12 3 4 1 000000 010001 010010 110011 2 000101 000000 000000 100010 3 000110 000000 000000 100001 4 001111 001010 001001 000000 the systolic delays are applied to the tudxs at the array periphery. in the first (or top) row, the sinl[8:0] and sinr[8:0] buses are delayed by 0, 5, 10, and 15 additional clock periods (moving from left to right across the first row). in the fourth (or bottom row, the doutl[8:0] and doutr[8:0] buses are delayed by 15, 10, 5, and 0 clock periods (again moving from left to right). in the first (or leftmost) column, the dint[8:0] and dinb[8:0] buses are delayed by 0, 5, 10, and 15 clock periods (moving from the top to the bottom of the first column). in the fourth (or rightmost) column, the soutt[8:0] and soutb[8:0] buses are delayed by 15, 10, 5, and 0 clock periods (again moving from top to bottom). the above array produces a 35 sclk cycle delay between the input and output busses.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 40 register 08h,0ch: connection address high bit type function default bit 7 r/w rwb x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 r/w cmp x bit 0 r/w ca8 x this register is used to trigger accesses to switching element connection memory and specify the memory location to be accessed. rwb: the rwb bit selects the type of connection memory access. the completion of a write access to this register will trigger a read of a switching element connection memory if rwb is high. if rwb is low, the completion of a write access to this register will trigger a write to a switching element connection memory. the data to be written or data read is passed through the connection data low and connection data high registers. the connection memory address and page to be accessed is determined by the connection address low and connection address high registers. a connection memory access requires several sclk cycles; completion of an access is indicated by the busy bit in the connection data high register. the instantiation of the connection address and data registers utilized selects the switching element to be programmed. registers 08h-0bh control the left switching element, and registers 0ch-0fh control the right switching element. cmp: the cmp bit, selects the connection memory page to be accessed. selection of which connection memory page is active is done using the page input or the connection memory control register. a logic 1 on this bit directs the read or write operation to the active page memory page. a logic 0 on this bit directs the read or write operation to the inactive memory page. accesses to the active cm memory page are likely to be much longer than accesses to the inactive memory page. this is because of the continual read accesses by
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 41 the internal timeslot counter to the active memory page. each cm page is broken into two independent banks of 135 x13. this increases the micro's access rate to active memory pages. ca8: the ca8 bit , together with the ca7-ca0 bits of the connection address low register selects the connection memory location to be accessed.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 42 register 09h,0dh: connection address low bit type function default bit 7 r/w ca7 x bit 6 r/w ca6 x bit 5 r/w ca5 x bit 4 r/w ca4 x bit 3 r/w ca3 x bit 2 r/w ca2 x bit 1 r/w ca1 x bit 0 r/w ca0 x this register is used to specify the memory location in switching element connection memory to be accessed. ca7-ca0: the ca7-ca0 bits , together with the ca8 bit of the connection address high register select the connection memory location to be accessed. connection memory locations correspond to outgoing timeslots on the doutl or doutr buses. each timeslot carries a 9 x 64 kbit/s channel corresponding to one column in a 270 x 9 byte sts-3 (or stm-1) frame. connection memory address 0 corresponds to the first column (the column that starts with the a1 byte of sts-1 #1 in an sts-3 stream) and address 269 corresponds to the last column (the column that ends with the last spe byte of sts-1 #3 in an sts-3 stream). see the sections on operation, functional timing, and application examples.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 43 register 0ah,0eh: connection data high bit type function default bit 7 r busy 0 bit 6 unused x bit 5 unused x bit 4 r/w cout x bit 3 r/w make x bit 2 r/w idle x bit 1 r/w top x bit 0 r/w cd8 x this register is used to detect when accesses to switching element connection memory are permitted and to pass data to connection memory during such accesses. busy: the busy bit allows one to detect when a connection memory access is permitted. when a switching element connection memory access is triggered by writing to the connection address high register, the busy bit is set high. the busy bit returns low when the access is complete. in the case of a write access, this means that one may begin manipulation of the various registers in preparation for a subsequent access. in the case of a read, this means that one may read valid data from the connection data high and low registers and then prepare for a subsequent access. while an access is in progress, i.e. when the busy bit is high, no new data should be written to any of the connection address or connection data registers. a connection memory access requires a maximum of ~400 ns (i.e. eight 19.44 mhz clock cycles). when a page swap is triggered via the connection memory control register or via the page input, the busy bit is also set high. at the next switch frame boundary (which can be up to ~ 14 us later) the page swap is implemented and the busy bit returns low. during this intervening time, while a page swap is pending, no new data should be written to any of the connection address or connection data registers. similarly, one should not trigger a
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 44 page swap until any previously initiated connection memory access is complete. cout: the cout bit controls one of the coutl or coutr signals during the corresponding outgoing timeslot on the doutl or doutr buses. by programming the cout bit, one can control the coutl or coutr signals on a per timeslot basis. the cout bit of the left switching element controls the coutl signal, the cout bit of the right switching element controls the coutr signal. make: the make bit enables a connection to be established through the switching element in question for the corresponding outgoing timeslot. when the make bit is set high, the switching element in question routes the corresponding timeslot onto the data path leading to the doutl or doutr buses, as appropriate. the source bus and timeslot to be connected are selected by the top bit and cd8-cd0 bits. when the make bit is set low, the switching element in question is held inactive to save power during the processing interval for the corresponding timeslot. when the make bit is set low, data entering on the sinl or sinr bus is routed to the doutl or doutr bus, as appropriate for the switching element in question. idle: the idle bit enables the insertion of programmable idle code into the corresponding outgoing timeslot. when the idle bit is set high, the switching element in question routes the connection data programmed through the cd8-cd0 bits onto the data path leading to the doutl or doutr buses, as appropriate. the mapping is cd7 to doutl[7] or doutr[7], cd6 to doutl[6] or doutr[6], and so on. cd8 is not mapped to doutl[8] or doutr[8]; doutl[8] and doutr[8] are parity bits generated by the tudx. in this case the connection data is not used to specify an incoming timeslot to be connected to an outgoing timeslot, but is used directly to form a programmable idle code. when the idle bit is set low, the switching element in question implements a normal time switching function. note that the idle bit has no effect unless the make bit is set high. top the top bit , selects the source of the connection to be established through the switching element in question for the corresponding outgoing timeslot. when top is high, the dint bus is selected. when top is low, the dinb bus
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 45 is selected. note that the top bit has no effect unless the make bit is set high. cd8 the cd8 bit , together with the cd7-cd0 bits of the connection data low register hold the connection memory data transferred during connection memory accesses. note that data read from the connection data high and low registers reflects the data read from the connection memories during the most recently triggered read operation. it typically does not reflect the last data written to these registers.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 46 register 0bh,0fh: connection data low bit type function default bit 7 r/w cd7 x bit 6 r/w cd6 x bit 5 r/w cd5 x bit 4 r/w cd4 x bit 3 r/w cd3 x bit 2 r/w cd2 x bit 1 r/w cd1 x bit 0 r/w cd0 x this register is used to pass data to connection memory during switching element connection memory accesses. cd7-cd0: the cd7-cd0 bits, together with the cd8 bit of the connection data high register hold the connection memory data transferred during connection memory accesses. connection memory data corresponds to incoming timeslots on the dint or dinb buses. each timeslot carries a 9 x 64 kbit/s channel corresponding to one column in a 270 x 9 byte sts-3 (or stm-1) frame. connection memory data of 0 corresponds to the first column (the column that starts with the a1 byte of sts-1 #1 in an sts-3 stream) and data of 269 corresponds to the last column (the column that ends with the last spe byte of sts-1 #3 in an sts-3 stream). connection memory data may also correspond to a programmable idle code. see the sections on operation, functional timing, and application examples. note that data read from the connection data high and low registers reflects the data read from the connection memories during the most recently triggered read operation. it typically does not reflect the last data written to these registers.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 47 11 test features description simultaneously asserting the cs1b, cs2b, rdb and wrb inputs low causes all output pins and the data bus to be held in a high-impedance state, provided that the mbeb input is held high. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the tudx. test mode registers (as opposed to normal mode registers) are selected when trs (a[4]) is high. test mode registers may also be used for board testing. when all of the constituent telecom system blocks within the tudx are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "test mode 0" for details). table 4 - test mode register memory map address register 00h-0fh normal mode registers 10h tudx master test 11h-13h input formatter test registers 14h-17h output formatter test registers 18h left switch element test register 0 19h left switch element test register 1 1ah left switch element test register 2 1bh left switch element test register 3 1ch right switch element test register 0 1dh right switch element test register 1 1eh right switch element test register 2 1fh right switch element test register 3 notes on test mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic 0. reading back unused bits
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 48 can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2. writable test mode register bits are not initialized upon reset unless otherwise noted.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 49 register 10h: master test bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 w pmctst x bit 3 w mototst 0 bit 2 r/w iotst 0 bit 1 w hizdata 0 bit 0 r/w hizio 0 this register is used to enable tudx test features. all bits, except pmctst, are reset to zero by a reset of the tudx. hizio,hizdata: the hizio and hizdata bits control the three state modes of the tudx . while the hizio bit is a logic 1, all output pins of the tudx except the data bus are held in a high-impedance state. the microprocessor interface is still active. while the hizdata bit is a logic 1, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles. iotst: the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each tsb block in the tudx for board level testing. when iotst is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the "i/o test mode details" in the "test features" section). mototst: the mototst bit is used to test the motorola interface. when mototst is logic 1 and the mbeb input is logic 0 the ofseb and sobeb inputs are used to replace the function of e and rwb, respectively. this is done because the fixed waveform shapes assigned to the rdb_e and wrb_rwb inputs can not be used to test motorola type microprocessor
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 50 interface logic. this mode is also used to test the d.c. drive capability of the d[7:0] device pins. pmctst: the pmctst bit is used to configure the tudx for pmc's manufacturing tests. when pmctst is set to logic 1, the tudx microprocessor port becomes the test access port used to run the pmc "canned" manufacturing test vectors. the pmctst bit is logically "ored" with the iotst bit, and can only be cleared by setting csb to logic 1.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 51 11.1 i/o test mode in the i/o test mode, the tudx allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface. to enable the i/o test mode, the iotst bit in the master test register is set to logic 1. reading the following address locations returns the values for the indicated inputs. table 5 - reading input pin values addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11h dint[7] dint[6] dint[5] dint[4] dint[3] dint[2] dint[1] dint[0] 12h dinb[7] dinb[6] dinb[5] dinb[4] dinb[3] dinb[2] dinb[1] dinb[0] 13h sclk ofseb sfp page sobeb dinb[8] dint[8] 14h sinr[7] sinr[6] sinr[5] sinr[4] sinr[3] sinr[2] sinr[1] sinr[0] 15h aobeb odeb sinl[8] 16h sinl[7] sinl[6] sinl[5] sinl[4] sinl[3] sinl[2] sinl[1] sinl[0] 17h aobeb odeb sinr[8] writing the following address locations forces the outputs to the value in the corresponding bit position: table 6 - forcing ouput pin values addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 11h sot[7] sot[6] sot[5] sot[4] sot[3] sot[2] sot[1] sot[0] 12h sob[7] sob[6] sob[5] sob[4] sob[3] sob[2] sob[1] sob[0] 13h intb ofp ifp sob[8] sot[8] 14h dor[7] dor[6] dor[5] dor[4] dor[3] dor[2] dor[1] dor[0] 15h coutl dol[8] 16h dol[7] dol[6] dol[5] dol[4] dol[3] dol[2] dol[1] dol[0] 17h coutr dor[8] soutt is abbreviated to sot to fit the above table. soutb is abbreviated to sob to fit the above table.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 52 doutl is abbreviated to dol to fit the above table. doutr is abbreviated to dor to fit the above table.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 53 12 operation 12.1 basic connection memory access 12.1.1 connection memory read to perform a connection memory read, one selects an address in the range 0- 269, encodes this as a 9 bit binary value and writes the lower 8 bits of this value into the connection address low register. the upper bit of this address is then written into the connection address high register while also setting the rwb bit in the connection address high register to 1 and selecting the desired connection memory page. the trailing edge of the write to the connection address high register triggers the internal connection memory access by the tudx and a read access is performed due to the rwb bit being a 1. the access requires up to ~400 ns to complete and one must wait this long or poll the busy bit in the connection data high register to determine that the access has completed. once the access has completed as indicated by the busy bit going low, one can then read valid data in the connection data high and low registers which was extracted during the just completed connection memory read access. note that once a connection memory read access is triggered by writing to the connection address high register, no further changes should be made to the connection address high or low registers until the access has completed. similarly, prior to initiating any read access, one must ensure that any previously triggered access or page swap has completed before one begins to alter relevant register contents. 12.1.2 connection memory write to perform a connection memory write, one selects the data to be written and writes this data into the connection data high and low registers. one then selects an address in the range 0-269, encodes this as a 9 bit binary value and writes the lower 8 bits of this value into the connection address low register. the upper bit of this address is then written into the connection address high register while also setting the rwb bit in the connection address high register to 0 and selecting the desired connection memory page. the trailing edge of the write to the connection address high register triggers the internal connection memory access by the tudx and a write access is performed due to the rwb bit being a 0. the access requires up to ~400 ns to complete and one must wait this long or poll the busy bit in the connection data high register to determine that the access has completed. once the access has completed as indicated by the busy bit going low, one is free to begin set up for subsequent accesses.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 54 note that once a connection memory write access is triggered by writing to the connection address high register, no further changes should be made to the connection address high or low registers or the connection data high or low registers until the access has completed. similarly, prior to initiating any write access, one must ensure that any previously triggered access or page swap has completed before one begins to alter relevant register contents. 12.2 connection set up to set up a connection, one must program connections for all of the 9 x 64 kbit/s timeslots that together constitute the tributary being connected. in the case of a vt1.5 or tu11, three connections must be programmed; in the case of a vt2 or tu12, four connections; and in the case of a vt6 or tu2, twelve connections. any channel or tributary that can be constructed as a multiple of the basic 9 x 64 kbit/s timeslot may be switched using group connections. to illustrate connection set up, consider the steps required to set up a vt1.5 cross-connection. for example, consider cross-connecting vt1.5 #1 of vt group #1 in sts-1 #1 of the sts-3 stream on the dint bus to vt1.5 #4 of vt group #7 in sts-1 #3 of the sts-3 stream on the doutl bus. the incoming vt1.5 occupies the 13th, 100th, and 187th columns in the sts-3 frame as shown in figure 1. the outgoing vt1.5 occupies the 96th, 183rd and 270th columns in the sts-3 frame. to make the connection one must connect each incoming timeslot occupied by the incoming vt1.5 to each outgoing timeslot occupied by the outgoing vt1.5 in the order in which the timeslots are utilized, i.e. 13th timeslot to 96th timeslot, 100th timeslot to 183rd timeslot, and 187th timeslot to 270th timeslot. the information that must be written to the connection address and connection data registers of the left switching element is as follows:
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 55 table 7 - connection set up connection address connection data connection/notes 005fh 0a0ch 13th timeslot cross connects to 96th timeslot ca=95, cd=12 cout=0, make=1, idle=0, top=1 00b6h 0963h 100th timeslot cross connects to 183rd timeslot ca=182, cd=99 cout=0, make=1, idle=0, top=1 010dh 09bah 187th timeslot cross connects to 270th timeslot ca=269, cd=186 cout=0, make=1, idle=0, top=1 figure 6 - sonet sts-3 carrying vt1.5 within sts-1 a1 a1 a1 a2 a2 a2 c1 c1 c1 poh poh poh spe spe spe spe b1 - - e1 - - f1 - - poh poh poh spe spe spe spe d1 - - d2 - - d3 - - poh poh poh spe spe spe spe h1 h1 h1 h2 h2 h2 h3 h3 h3 poh poh poh spe spe spe spe b2 b2 b2 k1 - - k2 - - poh poh poh spe spe spe spe d4 - - d5 - - d6 - - poh poh poh spe spe spe spe d7 - - d8 - - d9 - - poh poh poh spe spe spe spe d10 - - d11 - - d12 - - poh poh poh spe spe spe spe z1 - - z2 - - e2 - - poh poh poh spe spe spe spe row 1 2 3 4 5 6 7 8 9 col 123456789101112131415 270 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 265 266 spe spe spe spe spe spe spe spe spe 267 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 268 269 ? ? ? ? first of 3 columns occupied by vt1.5 #1 of vt group #1 of sts-1 #1 of an sts-3 stream (column set is 13, 100, 187) last of 3 columns occupied by vt1.5 #4 of vt group #7 of sts-1 #3 of an sts-3 stream (column set is 96, 183, 270)
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 56 figure 7 - sdh stm-1 carrying tu12 within vc3/au3 a1 a1 a1 a2 a2 a2 c1 c1 c1 poh poh poh spe spe spe spe b1 - - e1 - - f1 - - poh poh poh spe spe spe spe d1 - - d2 - - d3 - - poh poh poh spe spe spe spe h1 h1 h1 h2 h2 h2 h3 h3 h3 poh poh poh spe spe spe spe b2 b2 b2 k1 - - k2 - - poh poh poh spe spe spe spe d4 - - d5 - - d6 - - poh poh poh spe spe spe spe d7 - - d8 - - d9 - - poh poh poh spe spe spe spe d10 - - d11 - - d12 - - poh poh poh spe spe spe spe z1 - - z2 - - e2 - - poh poh poh spe spe spe spe row 1 2 3 4 5 6 7 8 9 col 123456789101112131415 270 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 265 266 spe spe spe spe spe spe spe spe spe 267 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 268 269 ? ? ? ? first of 4 columns occupied by tu12 #1 of tug2 #1 of vc3/ au3 #1 of an stm-1 stream (column set is 13, 76,142, 208) last of 4 columns occupied by tu12 #3 of tug2 #7 of vc3/ au3 #3 of an stm-1 stream (column set is 75, 141, 207, 270) figure 8 - sdh stm-1 carrying tu12 within tug3 a1 a1 a1 a2 a2 a2 c1 c1 c1 poh spe spe spe spe spe b1 - - e1 - - f1 - - poh spe spe spe spe spe d1 - - d2 - - d3 - - poh spe spe spe spe spe h1 h1 h1 h2 h2 h2 h3 h3 h3 poh spe spe spe spe spe b2 b2 b2 k1 - - k2 - - poh spe spe spe spe spe d4 - - d5 - - d6 - - poh spe spe spe spe spe d7 - - d8 - - d9 - - poh spe spe spe spe spe d10 - - d11 - - d12 - - poh spe spe spe spe spe z1 - - z2 - - e2 - - poh spe spe spe spe spe row 1 2 3 4 5 6 7 8 9 col 1234567891011 192021 270 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 265 266 spe spe spe spe spe spe spe spe spe 267 spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe spe 268 269 ? ? ? ? first of 4 columns occupied by tu12 #1 of tug2 #1 of tug3 #1 of an stm-1 stream (column set is 19, 82, 145, 208) last of 4 columns occupied by tu12 #3 of tug2 #7 of tug3 #3 of an stm-1 stream (column set is 81, 144, 207, 270) ? ? ? ? 12.3 idle code insertion to enable idle code insertion, one must program idle code insertion for all of the 9 x 64 kbit/s timeslots that together constitute the tributary being affected. in the case of a vt1.5 or tu11, three insertions must be programmed; in the case of a vt2 or tu12, four insertions; and in the case of a vt6 or tu2, twelve insertions. any channel or tributary that can be constructed as a multiple of the basic 9 x 64 kbit/s timeslot may be overwritten with idle code using a group insertion. to illustrate idle code insertion set up, consider the steps required to set up idle code insertion into a tu12. for example, consider inserting idle code into tu12 #1 of tug2 #1 in vc3/au3 #1 of the stm-1 stream on the doutr bus. the outgoing tu12 occupies the 13th, 76th, 142nd and 208th columns in the stm-1
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 57 frame. to enable idle code insertion one must program idle code insertion for each outgoing timeslot occupied by the outgoing tu12. one would normally program the same idle code value for all timeslots occupied by the tu12 and choose a value that results in a useful status indication in the tu12, such as all ones for tributary path ais. the information that must be written to the connection address and connection data registers of the right switching element is as follows: table 8 - idle code insertion connection address connection data connection/notes 000ch 0dffh all ones inserted into 13th timeslot ca=12, cd=all ones cout=0, make=1, idle=1, top=0 004bh 0dffh all ones inserted into 76th timeslot ca=75, cd=all ones cout=0, make=1, idle=1, top=0 008dh 0dffh all ones inserted into 142nd timeslot ca=141, cd=all ones cout=0, make=1, idle=1, top=0 00cfh 0dffh all ones inserted into 208th timeslot ca=207, cd=all ones cout=0, make=1, idle=1, top=0
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 58 13 functional timing the dint, dinb, sinl and sinr buses are nominally frame aligned, as are the doutl, doutr, soutt, and soutb buses. this alignment may be altered for use in systolic array applications when required. there is nominally a five clock cycle offset between the frame alignment of the input buses and the output buses. the sfp input, which synchronizes the frame alignment of the tudx pcm buses, can be configured to mark the frame alignment of either the input or output buses, depending on the strapping of the ofseb input. the timing of the aoutl and aoutr buses is identical to that of the doutl and doutr buses, respectively.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 59 figure 9 - input/output bus timing (systolic delay disabled) sclk ifp dint[8:0] a1 a1 a2 a2 a2c1 c1 c1 a1 dinb[8:0] a1 a1 a2 a2 a2c1 c1 c1 a1 sfp (ofseb=0) ofp doutl[8:0]/ aoutl[8:0] a1 a1 a2 a2 a2c1 c1 c1 a1 doutr[8:0]/ aoutr[8:0] a1 a1 a2 a2 a2c1 c1 c1 a1 sinl[8:0] a1 a1 a2 a2 a2c1 c1 c1 a1 sinr[8:0] a1 a1 a2 a2 a2c1 c1 c1 a1 soutt[8:0] a1 a1 a2 a2 a2c1 c1 c1 a1 soutb[8:0] a1 a1 a2 a2 a2c1 c1 c1 a1 sfp (ofseb=1) the input/output bus timing diagram (figure 9) illustrates the frame alignment through the tudx when the programmable systolic delay is set to zero for every bus. sfp must occur once every sonet/sdh frame (9 rows), and is illustrated marking the c1 byte position in the incoming stream (dint, dinb) or the outgoing stream (soutt, soutb) as selected by the ofseb input. output ofp always marks the c1 byte position in the soutt and soutb streams. ofp marks the c1 byte position in the doutl/doutr streams when a cross- connection has not been made through the device (the sinl/sinr streams flow
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 60 through the tudx without modification). if a cross connection is made between the dint/dinb streams and the doutl/doutr streams, then the data on doutl and doutr is delayed by 270 bytes due to the cross connection delay. in figure 4, output ofp would mark the e2 byte position in the sonet/sdh frame (i.e. the row immediately before the c1 row) if a cross connection is made between dint/dinb and doutl/doutr. figure 10 - input/output bus timing (systolic delay applied to sinl/sinr) sclk ifp dint[8:0] dinb[8:0] ofp doutl[8:0]/ aoutl[8:0] doutr[8:0]/ aoutr[8:0] sinl[8:0] sinr[8:0] soutt[8:0] soutb[8:0] sfp (ofseb=1) c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 10 11 12 13 14 15 c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 10 11 12 13 14 15 7+n 7+n c1 c1 c1 a2 a2 a2 26927012345678910 c1 c1 c1 a2 a2 a2 26927012345678910 c1 c1 c1 a2 a2 a2 26927012345678910 c1 c1 c1 a2 a2 a2 26927012345678910 the input/output bus timing diagram (figure 10) illustrates the frame alignment through the tudx when the programmable systolic delay is applied to the
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 61 sinl/sinr buses. it is assumed that a cross connection has not been made through the device (the doutl/doutr streams are delayed versions of the sinl/sinr streams). the sinl/sinr streams are delayed by n bytes (n=0, 5, 10, or 15) depending on the value programmed in the systolic delay control register. this delay may be used in systolic array applications where the sinl/sinr streams must be offset as they enter the array through the first (or top) row. figure 11 - input/output bus timing (systolic delay applied to dint/dinb) sclk ifp dint[8:0] dinb[8:0] ofp doutl[8:0]/ aoutl[8:0] doutr[8:0]/ aoutr[8:0] sinl[8:0] sinr[8:0] soutt[8:0] soutb[8:0] sfp (ofseb=1) c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 10 11 12 13 14 15 c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 10 11 12 13 14 15 7+n 7+n c1 c1 c1 a2 a2 a2 269 270 1 2 3 4 5 6 7 8 9 10 c1 c1 c1 a2 a2 a2 269 270 1 2 3 4 5 6 7 8 9 10 c1 c1 c1 a2 a2 a2 269 270 1 2 3 4 5 6 7 8 9 10 c1 c1 c1 a2 a2 a2 269 270 1 2 3 4 5 6 7 8 9 10
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 62 the input/output bus timing diagram (figure 11) illustrates the frame alignment through the tudx when the programmable systolic delay is applied to the dint/dinb buses. it is assumed that a cross connection has not been made through the device (the doutl/doutr streams are delayed versions of the sinl/sinr streams). the dint/dinb streams are delayed by n bytes (n=0, 5, 10, or 15) depending on the value programmed in the systolic delay control register. this delay may be used in systolic array applications where the dint/dinb streams must be offset as they enter the array through the first (or leftmost) column. figure 12 - input/output bus timing (systolic delay applied to doutl/doutr) sclk ifp dint[8:0] dinb[8:0] ofp doutl[8:0]/ aoutl[8:0] doutr[8:0]/ aoutr[8:0] sinl[8:0] sinr[8:0] soutt[8:0] soutb[8:0] sfp (ofseb=1) c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 10 11 12 13 14 15 c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 10 11 12 13 14 15 c1 c1 c1 a2 a2 a2 269 270 1 2 3 4 5 6 7 8 9 10 c1 c1 c1 a2 a2 a2 269 270 1 2 3 4 5 6 7 8 9 10 c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 10 11 12 13 14 15 c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 10 11 12 13 14 15 7-n 7-n
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 63 the input/output bus timing diagram (figure 13) illustrates the frame alignment through the tudx when the programmable systolic delay is applied to the doutl/doutr buses. it is assumed that a cross connection has not been made through the device (the doutl/doutr streams are delayed versions of the sinl/sinr streams). the doutl/doutr streams are delayed by n bytes (n=0, 5, 10, or 15) depending on the value programmed in the systolic delay control register. this delay may be used in systolic array applications where the doutl/doutr streams must be aligned as they exit the array from the last (or bottom) row.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 64 figure 13 - input/output bus timing (systolic delay applied to soutt/soutb) sclk ifp dint[8:0] dinb[8:0] ofp doutl[8:0]/ aoutl[8:0] doutr[8:0]/ aoutr[8:0] sinl[8:0] sinr[8:0] soutt[8:0] soutb[8:0] sfp (ofseb=1) c1 c1 c1 a2 a2 a2 4 5 6 7 8 9 12+n c1 c1 c1 a2 a2 a2 456789 c1 c1 c1 a2 a2 269 270 1 2 3 4 7+n c1 c1 c1 a2 269 270 1 2 3 4 c1 c1 c1 a2 4-n 7 8 9 10 c1 c1 c1 a2 4-n 7 8 9 10 c1 c1 c1 a2 a2 a2 456789 c1 c1 c1 a2 a2 a2 456789 6 6 7+n 12+n 12+n 12+n a2 the input/output bus timing diagram (figure 13) illustrates the frame alignment through the tudx when the programmable systolic delay is applied to the soutt/soutb buses. it is assumed that a cross connection has not been made through the device (the doutl/doutr streams are delayed versions of the sinl/sinr streams). the soutt/soutb streams are delayed by n bytes (n=0, 5, 10, or 15) depending on the value programmed in the systolic delay control register. this offset may be used in systolic array applications where the
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 65 soutt/soutb streams must be delayed as they exit the array through the last (or rightmost) column. this timing diagram differs from the previous three systolic delay timing diagrams in that the output frame pulse (ofp) is delayed identically to the soutt/soutb buses through the tudx. ofp is delayed so that each outgoing frame pulse from the last (or rightmost) column marks the correct frame position in the soutt/soutb buses. figure 14 - page timing sclk sfp page valid dint/dinb col 269 col 270 a1 a2 a1 a1 a2 a2 c1 the page timing diagram (figure 14) illustrates the sampling of the page input relative to the 270 byte row. the tudx samples page once per row during column 269 as illustrated (it is assumed that no systolic delay is applied to the dint/dinb buses). page is always sampled eight sclk periods before sfp is sampled (note that sfp must be set high once every nine rows while page is sampled once every row). in systolic array applications, the individual tudx frame alignments are offset. these frame alignment offsets must be taken into account when changing the page input to ensure coherent connection memory page selection.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 66 14 absolute maximum ratings table 9 - tudx maximum ratings ambient temperature under bias -40c to +85c storage temperature -40c to +125c supply voltage -0.5v to +6.0v voltage on any pin -0.5v to v dd +0.5v static discharge voltage 500 v latch-up current 100 ma dc input current 20 ma lead temperature + 230 c absolute maximum junction temperature +150c power dissipation 1.5 w
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 67 15 d.c. characteristics (t a = -40c to +85c, v dd = 5 v 10%) table 10 - tudx d.c. characteristics symbol parameter min typ max units conditions v il input low voltage -0.5 0.8 volts guaranteed input low voltage v ih input high voltage 2.0 v dd +0.5 volts guaranteed input high voltage v ol output or bidirectional low voltage 0.4 volts v dd = min, i ol = 4 ma for d[7:0] and intb, 8 ma for doutl[8:0], doutr[8:0], aoutl[8:0], and aoutr[8:0] and 2 ma for all others, note 3 v oh output or bidirectional high voltage 2.4 volts v dd = min, i oh = 4 ma for d[7:0], 8 ma for doutl[8:0], doutr[8:0], aoutl[8:0], and aoutr[8:0] and 2 ma for all others, note 3 v t+ reset input high voltage 4.0 3.2 volts v t- reset input low voltage 0.8 volts v th reset input hysteresis voltage 0.5 volts i ilpu input low current +20 +20 0 a v il = gnd, notes 1, 3 i ihpu input high current -10 0 a v ih = v dd , notes 1, 3
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 68 symbol parameter min typ max units conditions i ilpd input low current 0 +10 a v il = gnd, notes 4, 3 i ihpd input high current -200 -20 a v ih = v dd , notes 4, 3 i il input low current 0 +10 a v il = gnd, notes 2, 3 i ih input high current -10 0 a v ih = v dd , notes 2, 3 c in input capacitance 5 pf excluding package, package typically 2 pf c out output capacitance 5 pf excluding package, package typically 2 pf c io bidirectional capacitance 5 pf excluding package, package typically 2 pf i ddop1 operating current all connections 150 ma v dd = 5.5 v, outputs unloaded, sclk = 19.44 mhz, alternating data, all connections i ddop2 operating current switching elements not enabled 50 ma v dd = 5.5 v, outputs unloaded, sclk = 19.44 mhz, alternating data, switching elements not enabled
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 69 notes on d.c. characteristics: 1. input pin or bidirectional pin with internal pull-up resistor. 2. input pin or bidirectional pin without internal pull-up resistor 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. input pin or bidirectional pin with internal pull-down resistor.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 70 16 microprocessor interface timing characteristics (t a = -40c to +85c, v dd = 5 v 10%) table 11 - microprocessor interface read access (figure 15, figure 16) symbol parameter min max units ts ar address to valid read set-up time 25 ns th ar address to valid read hold time 20 ns ts alr address to latch set-up time 20 ns th alr address to latch hold time 20 ns tv l valid latch pulse width 20 ns ts rwb rwb to valid read set-up time 25 ns th rwb rwb to valid read hold time 20 ns ts lr latch to read set-up 0 ns th lr latch to read hold 20 ns tp rd valid read to valid data propagation delay 80 ns tz int valid intb de-asserted to output hi-z 50 ns tz rd valid read de-asserted to output hi-z 20 ns
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 71 figure 15 - microprocessor interface read access timing for intel mode intb tz int (cs1b+cs2b+rdb) valid data d[7:0] tp rd tz rd ts ar valid address a[4:0] ale tv l ts lr th alr th lr ts alr th ar notes on microprocessor interface read timing in intel mode: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the cs1b, cs2b and the rdb signals. 4. microprocessor interface timing applies to normal mode register accesses only. 5. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alr , th alr , tv l , and ts lr are not applicable. 6. parameter th ar and ts ar are not applicable if address latching is used. 7. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 72 8. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. figure 16 - microprocessor interface read access timing for motorola mode intb tz int (!cs1b&!cs2b&e) valid data d[7:0] tp rd tz rd valid address a[4:0] ale ts alr tv l ts lr th alr th lr th ar rwb ts rwb th rwb ts ar notes on microprocessor interface read timing in motorola mode: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]).
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 73 3. a valid read cycle is defined as a logical and of the inverted cs1b, the inverted cs2b and the rdb signals. 4. microprocessor interface timing applies to normal mode register accesses only. 5. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alr , th alr , tv l , and ts lr are not applicable. 6. parameter th ar and ts ar are not applicable if address latching is used. 7. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 8. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. table 12 - microprocessor interface write access (figure 17, figure 18) symbol parameter min max units ts aw address to valid write set-up time 25 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 20 ns th alw address to latch hold time 20 ns ts rwb rwb to valid write set-up time 25 ns th rwb rwb to valid write hold time 20 ns tv l valid latch pulse width 20 ns ts lw latch to write set-up 0 ns th lw latch to write hold 20 ns th dw data to valid write hold time 20 ns th aw address to valid write hold time 20 ns tv wr valid write pulse width 40 ns
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 74 figure 17 - microprocessor interface write access timing for intel mode th dw valid data d[7:0] tv wr ts dw (cs1b+cs2b+wrb) a[4:0] valid address ale tv l ts alw ts lw th alw th lw ts aw th aw notes on microprocessor interface write timing in intel mode: 1. a valid write cycle is defined as a logical or of the cs1b, cs2b and wrb. 2. microprocessor interface timing applies to normal mode register accesses only. 3. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alw , th alw , tv l , and ts lw are not applicable. 4. parameters th aw and ts aw are not applicable if address latching is used. 5. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 75 figure 18 - microprocessor interface write access timing for motorola mode tv wr (!cs1b&!cs2b&e) a[4:0] valid address th dw valid data d[7:0] ts dw ale tv l ts alw ts lw th alw th lw th aw ts aw rwb ts rwb th rwb notes on microprocessor interface write timing in motorola mode: 1. a valid write cycle is defined as a logical and of the inverted cs1b, inverted cs2b and the e signal when rwb is low. 2. microprocessor interface timing applies to normal mode register accesses only. 3. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alw , th alw , tv l , and ts lw are not applicable. 4. parameters th aw and ts aw are not applicable if address latching is used. 5. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 6. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 76 7. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 77 17 tudx timing characteristics (t a = -40c to +85c, v dd = 5 v 10%) table 13 - tudx input (figure 19) symbol description min max units sclk frequency (nominally 19.44mhz ) 20 mhz sclk duty cycle 40 60 % ts din din set-up time 4 ns th din din hold time 3 ns ts sfp sfp set-up time 4 ns th sfp sfp hold time 3 ns ts pa g e page set-up time 4 ns th pa g e page hold time 3 ns
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 78 figure 19 - input timing ts sfp th sfp sfp ts din th din dint[8:0] ts din th din dinb[8:0] sclk ts din th din sinl[8:0] ts din th din sinr[8:0] ts page th page page notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 79 table 14 - tudx output (figure 20) load = 60 pf, including 10 pf output capacitance. symbol description min max units tpcout sclk high to cout valid propagation delay 525ns tpfp sclk high to fp valid propagation delay 525ns table 15 - systolic output configuration odeb = 1, aobeb = 1, load = 60 pf, including 10 pf output capacitance. symbol description min max units tpdout sclk high to dout valid propagation delay 540ns table 16 - bused output configuration odeb = 0, aobeb = 1, load = 600 ohm pullup and 50 pf , including 10 pf output capacitance. symbol description min max units tpdout sclk high to dout valid propagation delay 540ns table 17 - parallel bused output configuration odeb = 0, aobeb = 0, load = 300 ohm pullup and 100 pf , including 20 pf output capacitance due to parallel dout/aout output connection. symbol description min max units tpdout sclk high to dout valid propagation delay 540ns
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 80 figure 20 - output timing tp dout doutl[8:0]/ aoutl[8:0] tp cout coutl tp dout doutr[8:0]/ aoutr[8:0] sclk tp cout coutr tp dout soutt[8:0] tp dout soutb[8:0] tp fp ifp tp fp ofp notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output signal in the
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 81 systolic application and to the 2.4 volt point of the output signal in the bused (open drain) applications.
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 82 18 ordering and thermal information table 18 - ordering pm5372-ri part no. description PM5371-RI 160 pin copper leadframe metric quad flat pack (mqfp) part no. ambient temperature theta ja theta jc PM5371-RI -40c to 85c 45 c/w 13 c/w
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 83 19 mechanical information figure 21 - metric quad flat pack C mqfp (body 28x28x3.49mm) e d d1 1 designator pin 1 e1 e 160 0.65 0.10 0.38 0.22 1.03 0.88 body size: ccc b e l e1 e d1 d a2 a1 a dim. max. min. nom. package type: 160 pin metric plastic quad flatpack-mqfp 3.42 4.07 0.25 0.39 3.17 3.42 30.95 31.20 31.45 27.85 28.00 28.10 30.95 31.20 31.45 27.85 28.00 28.10 0.73 8-12 deg a 8-12 deg a2 see detail a 3.68 28 x 28 x 3.49 mm gage plane, 0.25 above seating plane. detail a 0-7 deg plane seating 0.13-0.23 c l .25 a 0-10 deg. ccc c lead coplanarity notes: 1) all dimensions in millimeter. b standoff a1 3) foot length "l" is measured at c with tolerances as indicated. 2) dimensions shown are nominal
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect proprietary and confidential to pmc-sierra, inc., and for its customers internal use 84 notes
pm5371 tudx data sheet pmc-920525 issue 6 sonet/sdh tributary unit cross connect none of the information contained in this document constitutes an express or implied warranty by pmc-sierra, inc. as to the suf ficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchanta bility, performance, compatibility with other parts or systems, of any of the products of pmc-sierra, inc., or any portion thereof, referred to in this document. pmc-sierra, inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not l imited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. in no event will pmc-sierra, inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not pmc-sierra, inc. has been advised of the possibility of such damage. ? 1998 pmc-sierra, inc. pmc-920525 (r6) ref pmc-920103 (r12) issue date: september 1998 proprietary and confidential to pmc-sierra, inc., and for its customers internal use contacting pmc-sierra, inc. pmc-sierra, inc. 105-8555 baxter place burnaby, bc canada v5a 4v7 tel: (604) 415-6000 fax: (604) 415-6200 document information: document@pmc-sierra.com corporate information: info@pmc-sierra.com application information: apps@pmc-sierra.com web site: http://www.pmc-sierra.com

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